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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\npc\Desktop\riscv\gao_yun_psram\src\IP\gowin_sp\RAM.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\riscv32.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\riscv32_alu.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\top.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\uart_debug.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\uart_memory.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\uart_recv.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\uart_txd.v<br>
C:\Users\npc\Desktop\riscv\gao_yun_psram\src\psram.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Jan 24 18:40:07 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 1s, Peak memory usage = 244.348MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 1s, Peak memory usage = 244.348MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 244.348MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.77s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 26s, Elapsed time = 0h 0m 36s, Peak memory usage = 244.348MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.977s, Peak memory usage = 244.348MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 244.348MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 30s, Elapsed time = 0h 0m 42s, Peak memory usage = 244.348MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>30</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1209</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>12</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>651</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>7</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>232</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>74</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>155</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFN</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDLC</td>
<td>64</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>3488</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>255</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1125</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2108</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>265</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>265</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>32</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>11</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>11</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSP</td>
<td>8</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>3956(3499 LUTs, 265 ALUs, 32 SSRAMs) / 8640</td>
<td>46%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1209 / 6693</td>
<td>18%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>64 / 6693</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1145 / 6693</td>
<td>17%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>8 / 26</td>
<td>31%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>n337_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F </td>
</tr>
<tr>
<td>n1001_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/n1001_s1/F </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.0(MHz)</td>
<td>72.2(MHz)</td>
<td>12</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n337_5[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>148</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I1</td>
</tr>
<tr>
<td>3.382</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>3.862</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>4.684</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>5.790</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>6.270</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_7_s0/RAD[3]</td>
</tr>
<tr>
<td>6.529</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_7_s0/DO[3]</td>
</tr>
<tr>
<td>7.009</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n336_s2/I1</td>
</tr>
<tr>
<td>8.108</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n336_s2/F</td>
</tr>
<tr>
<td>8.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n336_s0/I1</td>
</tr>
<tr>
<td>9.687</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n336_s0/F</td>
</tr>
<tr>
<td>10.167</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/G</td>
</tr>
<tr>
<td>10.450</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td>10.050</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.004, 56.721%; route: 3.360, 38.084%; tC2Q: 0.458, 5.195%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n337_5[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>148</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I1</td>
</tr>
<tr>
<td>3.382</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>3.862</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>4.684</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>5.790</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>6.270</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/RAD[3]</td>
</tr>
<tr>
<td>6.529</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/DO[0]</td>
</tr>
<tr>
<td>7.009</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n646_s2/I1</td>
</tr>
<tr>
<td>8.108</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n646_s2/F</td>
</tr>
<tr>
<td>8.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n646_s0/I1</td>
</tr>
<tr>
<td>9.687</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n646_s0/F</td>
</tr>
<tr>
<td>10.167</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/G</td>
</tr>
<tr>
<td>10.450</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td>10.050</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.004, 56.721%; route: 3.360, 38.084%; tC2Q: 0.458, 5.195%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n337_5[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>148</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I1</td>
</tr>
<tr>
<td>3.382</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>3.862</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>4.684</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>5.790</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>6.270</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/RAD[3]</td>
</tr>
<tr>
<td>6.529</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/DO[1]</td>
</tr>
<tr>
<td>7.009</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n636_s2/I1</td>
</tr>
<tr>
<td>8.108</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n636_s2/F</td>
</tr>
<tr>
<td>8.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n636_s0/I1</td>
</tr>
<tr>
<td>9.687</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n636_s0/F</td>
</tr>
<tr>
<td>10.167</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/G</td>
</tr>
<tr>
<td>10.450</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td>10.050</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.004, 56.721%; route: 3.360, 38.084%; tC2Q: 0.458, 5.195%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n337_5[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>148</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I1</td>
</tr>
<tr>
<td>3.382</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>3.862</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>4.684</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>5.790</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>6.270</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/RAD[3]</td>
</tr>
<tr>
<td>6.529</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>7.009</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n626_s2/I1</td>
</tr>
<tr>
<td>8.108</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n626_s2/F</td>
</tr>
<tr>
<td>8.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n626_s0/I1</td>
</tr>
<tr>
<td>9.687</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n626_s0/F</td>
</tr>
<tr>
<td>10.167</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/G</td>
</tr>
<tr>
<td>10.450</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td>10.050</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.004, 56.721%; route: 3.360, 38.084%; tC2Q: 0.458, 5.195%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.167</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n337_5[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.345</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/CLK</td>
</tr>
<tr>
<td>1.803</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>148</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_2_s0/Q</td>
</tr>
<tr>
<td>2.283</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I1</td>
</tr>
<tr>
<td>3.382</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>3.862</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>4.684</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>5.164</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>5.790</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>6.270</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/RAD[3]</td>
</tr>
<tr>
<td>6.529</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_0_s0/DO[3]</td>
</tr>
<tr>
<td>7.009</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n616_s2/I1</td>
</tr>
<tr>
<td>8.108</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n616_s2/F</td>
</tr>
<tr>
<td>8.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n616_s0/I1</td>
</tr>
<tr>
<td>9.687</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/n616_s0/F</td>
</tr>
<tr>
<td>10.167</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/G</td>
</tr>
<tr>
<td>10.450</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td>10.050</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.004, 56.721%; route: 3.360, 38.084%; tC2Q: 0.458, 5.195%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.982, 73.009%; route: 0.363, 26.991%</td></tr>
</table>
<br/>
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